A nitride-based semiconductor such as GAN, AlGaN, InGaN, InAlN, InAlGaN has a feature of high insulation breakdown strength, high thermal conductivity, and high electron saturated speed. For this feature, a nitride-based semiconductor material has great potential as a semiconductor material used for the manufacturing a power device for power controlling such as switching elements, or a high frequency device, and in recent years, the practical use development of a field effect transistor using the nitride-based semiconductor material has been actively performed.
For the application as above, the field effect transistor is required to be a normally-off (enhancement) type that does not require a negative direct-current bias power supply to a gate electrode of the field effect transistor. FIG. 8 shows an example of the structure proposed as a normally-off (enhancement) type field effect transistor using a nitride-based semiconductor material (see patent document 1). Hereinafter, the structure of the normally-off type field effect transistor using the nitride-based semiconductor according to the art exemplified in FIG. 8 is briefly described.
A buffer layer 12 and a channel layer 13 formed of i-GaN, for example, are laminated in this order on a semi-insulating substrate 11. On the channel layer 13, a first electron supply layer 14a and a second electron supply layer 14b formed of AlGaN, for example, whose band gap is larger than that of the channel layer 13 are formed to be isolated from each other. Also, on both sides, a pair of contact layers 16a, 16b formed of n-GaN, for example, where n-type impurities such as Si are doped with high density of 5×1017 cm−3 or more are formed. A source electrode S is formed on the contact layer 16a, and a drain electrode D is formed on the contact layer 16b. On the other hand, the surface of the channel layer 13 exposed between the first and the second electron supply layers 14a, 14b is coated with an insulating layer 15. Further, a gate electrode G formed of Ta—Si, for example, is formed, on the insulating layer 15, to form a gate region G0.
Since, in the gate region G0, an electron supply layer does not exist below the gate electrode G, there is no two-dimensional electron gas immediately below the gate electrode G, which is the channel layer 13 located between the first electron supply layer 14a and second the electron supply layer 14b. When a predetermined bias voltage is applied to the gate electrode G, an inversion distribution layer is generated in the channel layer 13 which is located immediately below the insulating layer 15. Because this inversion distribution layer connects between the two dimensions electron gases 6 generated below the first electron supply layer 14a and the second electron supply layer 14b, a drain current flows between the source electrode S and the drain electrode D, and the transistor is on.
On the other hand, neither the two-dimensional electron gas nor the inversion distribution layer is formed, immediately below the gate electrode G when the gate voltage is not biased (Vg=0V), and the two-dimensional electron gases 6 generated below the first electron supply layer 14a and the second electron supply layer 14b are disconnected with each other. Thus, in the state of Vg=0V, the drain current does not flow between the source electrode S and the drain electrode D. That is, the field effect transistor exemplified in FIG. 8 functions as so-called normally-off type transistor in which a drain current does not flow in a state of Vg=0V.
[Patent Document 1]
    Domestic Re-publication of PCT International Publication for Patent Application, No. WO 2003/071607